RIE-10

SPTS Rapier DRIE

Nanofabrication Facility

MAKE

Orbotech

MODEL

Omega LPX Rapier

LOCATION

LISE Cleanroom G07

SPTS Rapier DRIE (RIE-10) SPTS RIE-10, a state-of-the-art deep silicon etching system, is furnished with dual plasma sources and dual gas inlets. The tool is characterized with high etch rate 6-10 脙聜脗碌m/min; high aspect ratio 50:1; good selectivity > 50:1 to resist and >100:1 to silicon oxide; and a good uniformity < 5% cross 6脙垄芒聜卢脗聺 wafers. Its fixed RF matching technology reduces the step-process time to 1 second, which leads to a controllable side wall roughness < 6nm for nanoscale features. Major features include: 脙聜脗路 Primary rf power up to 3,000W 脙聜脗路 Secondary rf power up to 3,000W 脙聜脗路 Substrate power up to 300W 脙聜脗路 Chuck temperatures from -15脙聜脗掳C to +40脙聜脗掳C 脙聜脗路 Handling 6脙垄芒聜卢脗鲁 or smaller samples 脙聜脗路 Claritas End Point Detector Applications 脙聜脗路 Si etch only 脙聜脗路 High aspect ratio etch: 5 脙垄芒聜卢芒聙聹 50 脙聜脗路 Deep etch: 5脙聜脗碌m 脙垄芒聜卢芒聙聹 through Si wafer etch 脙聜脗路 Broad feature sizes: from nano- to mm- scales in lateral dimension 脙聜脗路 Side wall roughness (scallop depth): 6nm 脙垄芒聜卢芒聙聹 700nm 脙聜脗路 Only resists and SiO2 or Si3N4 allowed as etching mask 脙聜脗路 Handling 6脙垄芒聜卢脗鲁 or smaller samples 脙聜脗路 Absolutely no-metal mask or metal stop layers Available Processes 脙聜脗路 Micro Pillars 脙聜脗路 Nano Pillars 脙聜脗路 Micro Trenches 脙聜脗路 Nano Trenches 脙聜脗路 Via etch 脙聜脗路 Through wafer via etch 脙聜脗路 Wafer thinning

Click here to view this tool in the CNS virtual reality model.

Contact staff for training information.  Please refer to the Nanofabrication Facility Use tab of the User Info section of the CNS website for the nanofab training flowchart.

Ling Xie

lxie@cns.fas.harvard.edu

primary contact

David LaFleur

dlafleur@cns.fas.harvard.edu

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